The layout synthesizer: an automatic Netlist-to-Layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
GENAC: an automatic cell synthesis tool
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
XPRESS: A Cell Layout Generator with Integrated Transistor Folding
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Improved compaction by minimized length of wires
DAC '83 Proceedings of the 20th Design Automation Conference
Echelon: a multilayer detailed area router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Library-less synthesis for static CMOS combinational logic circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Direct transistor-level layout for digital blocks
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Accurate pre-layout estimation of standard cell characteristics
Proceedings of the 41st annual Design Automation Conference
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Exact minimum-width transistor placement without dual constraint for CMOS cells
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
Proceedings of the 24th symposium on Integrated circuits and systems design
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This paper describes a fully automatic standard-cell layoutsynthesis system, CELLERITY. The system is flexible insupporting a wide variety of process technologies and a range oflibrary template styles. The tool is fully automatic and providesseveral options to the user to customize the layout template. Thetool considers performance and yield and generates dense,design-rule correct layouts. Experimental results indicate that thearea of CELLERITY-generated standard cells is competitive withmanually designed cells in a majority of circuits. In block-leveltests of industrial circuits, standard-cell blocks generated usingCELLERITY cells are about equal to the block area produced byusing a manually-designed library. Recently, an embeddedmicrocontroller in a state-of-the-art sub-micron processtechnology was fabricated using CELLERITY-generated standard cells.