Layout optimization of CMOS functional cells
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An efficient layout style for 2-metal CMOS leaf cells and their automatic generation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Exact width and height minimization of CMOS cells
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Automatic layout synthesis of leaf cells
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Width minimization of two-dimensional CMOS cells using integer programming
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
CELLERITY: a fully automatic layout synthesis system for standard cell libraries
DAC '97 Proceedings of the 34th annual Design Automation Conference
The future of custom cell generation in physical synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
CLIP: an optimizing layout generator for two-dimensional CMOS cells
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimal 2-D cell layout with integrated transistor folding
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HAL: heuristic algorithms for layout synthesis
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
XPRESS: A Cell Layout Generator with Integrated Transistor Folding
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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We present a solution to the layout problem of cell synthesis, which achieves multiple optimization objectives. In particular, we propose a new hierarchical method for fast and optimal placement of the transistors in a cell. The method minimizes the number of diffusion breaks, and allows a further pursuit of a secondary optimization objective, such as routing channel density. For cells with non-uniform transistor widths, the transistors are folded in such a way as to optimize a cost function which is a good approximation to the area of the final(compacted) layout of the cell. We also analyze the characteristic nature of routing in cell generation problem, and design an algorithm for doing routing over the transistors; such routing reduces the routing channel density in the central region of the cell. The routing in the central region is completed by a new channel router at, or near, the channel density. The algorithms are implemented in a system call GENAC. The input to GENAC is a transistor net list, describing the connectivity as well as the size and type of each transistor. The output is a synthesized layout of the cell in symbolic language.