A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells

  • Authors:
  • Avaneendra Gupta;John P. Hayes

  • Affiliations:
  • -;-

  • Venue:
  • VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
  • Year:
  • 1997

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Abstract