Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Depth first search and dynamic programming algorithms for efficient CMOS cell generation
Proceedings of the fifth MIT conference on Advanced research in VLSI
The “PI” (placement and interconnect) system
DAC '82 Proceedings of the 19th Design Automation Conference
Use of domain knowledge in computer aid for ic cell layout design
Use of domain knowledge in computer aid for ic cell layout design
Template style considerations for sea-of-gates layout generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The layout synthesizer: an automatic Netlist-to-Layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Layout synthesis of MOS digital cells
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Exact width and height minimization of CMOS cells
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Routing considerations in symbolic layout synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automatic layout synthesis of leaf cells
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Width minimization of two-dimensional CMOS cells using integer programming
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The future of custom cell generation in physical synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
CLIP: an optimizing layout generator for two-dimensional CMOS cells
DAC '97 Proceedings of the 34th annual Design Automation Conference
AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HAL: heuristic algorithms for layout synthesis
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Transistor placement and interconnect algorithms for leaf cell synthesis
EURO-DAC '90 Proceedings of the conference on European design automation
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This paper describes SOLO, a program for mapping arbitrary MOS circuit schematics into efficient corresponding layouts. SOLO employs a layout strategy which allows it to be applied to circuits with sized transistors as well as to circuits which include unequal numbers of n-MOS and p-MOS transistors. The program can effectively be applied to module-size circuits including up to roughly 200 transistors.