Integer and combinatorial optimization
Integer and combinatorial optimization
GENAC: an automatic cell synthesis tool
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Logic-based 0-1 constraint programming
Logic-based 0-1 constraint programming
Width minimization of two-dimensional CMOS cells using integer programming
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
SOLO: a generator of efficient layouts from optimized MOS circuit schematics
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
XPRESS: A Cell Layout Generator with Integrated Transistor Folding
EDTC '96 Proceedings of the 1996 European conference on Design and Test
DAC '82 Proceedings of the 19th Design Automation Conference
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Optimal 2-D cell layout with integrated transistor folding
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
ISPD '99 Proceedings of the 1999 international symposium on Physical design
AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transistor placement for noncomplementary digital VLSI cell synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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We present a novel technique CLIP for optimizing both theheight and width of CMOS cell layouts in the two-dimensional (2-D) style. CLIP is based on integer-linear programming (ILP) and proceeds in two stages: First, an ILP model is used to determine a 2-D layout of minimum width W cell . Then, another model generatesa 2-D layout that has width W cell and requires a minimumnumber of routing tracks. Run times are in seconds for circuitswith up to 16 transistors. For larger circuits, we extend CLIP to ahierarchical method HCLIP that places series-connected transistorscontiguously. This reduces run times by up to three orders ofmagnitude, and still yields optimal results in over 80% of cases.