GENAC: an automatic cell synthesis tool
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Automatic layout synthesis of leaf cells
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A new layout synthesis for leaf cell design
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
CLIP: an optimizing layout generator for two-dimensional CMOS cells
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
SOLO: a generator of efficient layouts from optimized MOS circuit schematics
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Optimal diffusion sharing in digital and analog CMOS layout
Optimal diffusion sharing in digital and analog CMOS layout
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Transistor level placement for full custom datapath cell design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Automatic datapath tile placement and routing
Proceedings of the conference on Design, automation and test in Europe
Data path placement with regularity
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Direct transistor-level layout for digital blocks
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Transistor placement for noncomplementary digital VLSI cell synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic transistor and physical design of FPGA tiles from an architectural specification
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
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This paper describes AKORD, a transistor level and mixed transistor/gate level placement tool. AKORD has unique layout capabilities that address the digital data path layout problem. In order to improve communication between the placement and routing steps, new post placement algorithms were developed: a device re-spacing procedure, an optimization procedure for gate contacts, and a procedure which reduces wire crossovers. AKORD supports dynamically: 1. Transistor folding without usage of device libraries that contain variants of the same device; 2. Device merging, including information about optimal transistor chain formation; and 3. Well area minimization. Experimental results show that the automated layouts are comparable to skilled manual layouts and that the computation times are quite modest.