Transistor level placement for full custom datapath cell design

Authors:
Durgam Vahia;Maciej Ciesielski
Affiliations:
Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA;Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA
Venue:
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Year:
1999

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