Algorithms & data structures
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Automatic layout of low-cost quick-turnaround random-logic custom LSI devices
DAC '76 Proceedings of the 13th Design Automation Conference
LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
A 2-dimensional placement algorithm for the layout of electrical circuits.
DAC '76 Proceedings of the 13th Design Automation Conference
PRO - an automatic string placement program for polycell layout
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
A high quality, low cost router for MOS/LSI
DAC '72 Proceedings of the 9th Design Automation Workshop
DAC '82 Proceedings of the 19th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
Placement algorithm by partitioning for optimum rectangular placement
DAC '79 Proceedings of the 16th Design Automation Conference
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI
DAC '79 Proceedings of the 16th Design Automation Conference
Strip layout: a new layout methodology for standard circuit modules
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
GENAC: an automatic cell synthesis tool
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
An analytical approach to floorplan design and optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A data path layout assembler for high performance DSP circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Deriving efficient area and delay estimates by modeling layout tools
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal folding of standard and custom cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transistor level placement for full custom datapath cell design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
A probabilistic multicommodity-flow solution to circuit clustering problems
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
ALPS2: a standard cell layout system for double-layer metal technology
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Experiments with simulated annealing
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Simulated annealing and combinatorial optimization
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Modeling layout tools to derive forward estimates of area and delay at the RTL level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data path placement with regularity
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Parameterized algorithmics for linear arrangement problems
Discrete Applied Mathematics
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Given a set of interconnected elements, linear ordering generates a linear sequence of elements of the set, which is the basis for most constructive initial-placement methods. This paper presents a new strategy for linear ordering. The important difference of the new technique from the previous ones is that it starts the ordering process from the most lightly connected seed. It was applied to various placement problems including standard cell and gate array and produced very good results.