LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
PRO - an automatic string placement program for polycell layout
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
A high quality, low cost router for MOS/LSI
DAC '72 Proceedings of the 9th Design Automation Workshop
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic placement of rectangular blocks with the interconnection channels
DAC '81 Proceedings of the 18th Design Automation Conference
Hierarchical top-down layout design method for VLSI chip
DAC '82 Proceedings of the 19th Design Automation Conference
A two-dimensional placement algorithm for the master slice LSI layout problem
DAC '79 Proceedings of the 16th Design Automation Conference
A hierarchical placement procedure with a simple blocking scheme
DAC '79 Proceedings of the 16th Design Automation Conference
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PLAC is a multi-algorithm, 2-dimensional placement program which accommodates many of the “real world” constraints which occur in the layout of electrical circuits. PLAC was implemented as part of LTX [1], a general integrated circuit layout system, but is capable of handling circuit layout tasks from other technologies (e.g., PC boards, ceramic substrates). PLAC interlaces constructive initial placement with iterative pairwise exchange, using an approximation of total routing length as the primary figure-of-merit. The layout designer can influence the placement by providing a “seed” preplacement of key cells. PLAC results are given for a DIP board layout and two polycell integrated circuit layouts. Comparisons are made to other semi-automatic and manual placement procedures. Running time on an HP21MX minicomputer ranged from 4 minutes on a 34-cell problem to 1 hour on a 511-cell problem.