Some experimental results on placement techniques
DAC '76 Proceedings of the 13th Design Automation Conference
A 2-dimensional placement algorithm for the layout of electrical circuits.
DAC '76 Proceedings of the 13th Design Automation Conference
An iterative algorithm for placement and assignment of integrated circuits
DAC '75 Proceedings of the 12th Design Automation Conference
The chip layout problem: A placement procedure for lsi
DAC '77 Proceedings of the 14th Design Automation Conference
The chip layout problem: An automatic wiring procedure
DAC '77 Proceedings of the 14th Design Automation Conference
Placement of variable size circuits on LSI masterslices
DAC '81 Proceedings of the 18th Design Automation Conference
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This paper deals with the optimum placement of blocks on a two-dimensional cell-array, which minimizes the total routing length of signal sets. A new heuristic procedure, based on iterative improvement, is proposed. The procedure repeats random generation of an initial solution and its improvement by a sequence of local transformations. The best among the local optimum solutions is taken as a final solution. The iterative improvement method proposed here is different from the previous one in the sense that it considers interchanging more than two blocks at the same time and examines only a small portion of feasible solutions which has high probability of being better. Experimental results show this procedure gives better solutions than the best one up to now. The computation time for each local optimum solution grows almost linearly with regard to the number of blocks.