Some experimental results on placement techniques
DAC '76 Proceedings of the 13th Design Automation Conference
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
The chip layout problem: A placement procedure for lsi
DAC '77 Proceedings of the 14th Design Automation Conference
The chip layout problem: An automatic wiring procedure
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Initial design concepts for an advanced design automation system
DAC '74 Proceedings of the 11th Design Automation Workshop
A min-cut placement algorithm for general cell assemblies based on a graph representation
DAC '79 Proceedings of the 16th Design Automation Conference
A two-dimensional placement algorithm for the master slice LSI layout problem
DAC '79 Proceedings of the 16th Design Automation Conference
A hierarchical placement procedure with a simple blocking scheme
DAC '79 Proceedings of the 16th Design Automation Conference
A placement capability based on partitioning
DAC '79 Proceedings of the 16th Design Automation Conference
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Placement of irregular circuit elements on non-uniform gate arrays
DAC '83 Proceedings of the 20th Design Automation Conference
CGALA-a multi technology Gate Array Layout system
DAC '82 Proceedings of the 19th Design Automation Conference
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With the advent of large scale integration (LSI and VLSI), logic circuit densities per chip have grown to hundreds and thousands. The arrangement of interconnected logic circuits of different sizes and shapes poses a difficult combinatorial placement problem. In this paper, an overview of techniques is presented for placing different size rectangular circuits with limited locations on the chip, considering the function of level sensitive scan design (LSSD)1, as well as wirability and electrical constraints. The automatic placement program (APLACE), encompassing techniques to handle various constraints, was developed in IBM's Engineering Design System. An overview is presented of the technique for partitioning logic into clusters (supernodes) and breaking the image down into a rectangular grid (super locations) for initial placement.2 Iterative techniques that improve the initial placement and satisfy wirability and electrical (D.C. and capacitance) constraints are outlined. The concepts of zero ground interchange to balance horizontal and vertical channel demand and zonal movement to distribute wiring are presented. APLACE was developed primarily for the layout of the 704 gate masterslice used extensively in IBM's System 3081, encompassing 750,000 circuits. It has been in extensive use in IBM since the early 1970's to design thousands of masterslice chips ranging from 320-1500 circuits for IBM's System 38,3-4 System 4341,5 System 8100, for the 5000 gate array microprocessor6,7 and for many others. The automatic layout method, APLACE, reduces design cycle time considerably and requires little or no manual intervention.