A 2-dimensional placement algorithm for the layout of electrical circuits.
DAC '76 Proceedings of the 13th Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A heuristic procedure for ordering MOS arrays
DAC '75 Proceedings of the 12th Design Automation Conference
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing
DAC '81 Proceedings of the 18th Design Automation Conference
Placement of variable size circuits on LSI masterslices
DAC '81 Proceedings of the 18th Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
A consideration of the number of horizontal grids used in the routing of a masterslice layout
DAC '82 Proceedings of the 19th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
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The outline of a hierarchical placement procedure utilizing a simple blocking scheme is described with the results of the application to the DSA-MOS gate arrays. Indirect clustering value is introduced for the blocking, i.e. grouping of modules under block size restriction. The system including the procedure has been successfully applied to the design of MOS gate arrays with effectively no manual assistance.