Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Graphs and Hypergraphs
Automatic layout algorithms for function blocks of CMOS gate arrays
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A layout system for the random logic portion of MOS LSI
DAC '80 Proceedings of the 17th Design Automation Conference
A hierarchical placement procedure with a simple blocking scheme
DAC '79 Proceedings of the 16th Design Automation Conference
A Layout System for the Random Logic Portion of an MOS LSI Chip
IEEE Transactions on Computers
An automatic cell pattern generation system for CMOS transistor-pair array LSI
Integration, the VLSI Journal
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For automated layout of one-dimensional MOS gates arrays, a heuristic procedure, determining the optimal ordering of gates to minimize the chip area, is presented.