Logic Design and Switching Theory
Logic Design and Switching Theory
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
SHARPS: A hierarchical layout system for VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A heuristic procedure for ordering MOS arrays
DAC '75 Proceedings of the 12th Design Automation Conference
Computer-Aided Preliminary Layout Design of Customized MOS Arrays
IEEE Transactions on Computers
Hi-index | 14.98 |
The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multiphase clocking system, and occupies ordinarily a considerable part of chip area. In this paper a layout system for this portion of an LSI chip is described, which is constructed on the basis of heuristics for a set of interrelated optimization problems. Implementation results of the layout system are also shown to reveal that the random logic portion can be realized in such an areas as comparable to one done by manual layout.