A layout system for the random logic portion of MOS LSI
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Placement and routing algorithms for hierarchical integrated circuit layout
Placement and routing algorithms for hierarchical integrated circuit layout
A channel/switchbox definition algorithm for building-block layout
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On minimizing the number of L-shaped channels
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Placement algorithms for custom VLSI
DAC '83 Proceedings of the 20th Design Automation Conference
SAGA: An Experimental Silicon Assembler
DAC '82 Proceedings of the 19th Design Automation Conference
A placement algorithm for polycell LSI and ITS evaluation
DAC '82 Proceedings of the 19th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
A Layout System for the Random Logic Portion of an MOS LSI Chip
IEEE Transactions on Computers
Placement algorithms for custom VLSI
Computer-Aided Design
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A hierarchical layout system for VLSI provided with placement and routing facilities is described, highlighting the routing scheme constructed on the basis of a channel router. Several implementation results are also shown to reveal how much the system has potentialities to be of great use in the practice of layout design of full custom LSI's.