SHARPS: A hierarchical layout system for VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
A min-cut placement algorithm for general cell assemblies based on a graph representation
DAC '79 Proceedings of the 16th Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Clustering based simulated annealing for standard cell placement
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
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An automatic placement algorithm for standard cell and polycell LSI is described, which is constructed on the basis of heuristics for a set of interrelated placement subproblems. The algorithm is incorporated into a hierarchical layout system intended not only for standard cell and polycell LSI but for general cell LSI, by which standard cell and polycell LSI have begun to be laid out in practice. A part of implementation results are also shown to reveal how high the layout performance of the placement program.