Standard cell placement using simulated sintering
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement algorithms for high packing density V L S I
DAC '83 Proceedings of the 20th Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
A placement algorithm for polycell LSI and ITS evaluation
DAC '82 Proceedings of the 19th Design Automation Conference
A comparison of four two-dimensional gate matrix layout tools
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
A Parallel Simulated Annealing Algorithm with Low Communication Overhead
IEEE Transactions on Parallel and Distributed Systems
A combined hierarchical placement algorithm
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A timing driven N-way chip and multi-chip partitioner
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
An effective general connectivity concept for clustering
Proceedings of the conference on Design, automation and test in Europe
Local search for final placement in VLSI design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Evaluating Label Placement for Augmented Reality View Management
ISMAR '03 Proceedings of the 2nd IEEE/ACM International Symposium on Mixed and Augmented Reality
Evolutionary Computation - Special issue on magnetic algorithms
Design flow and methodology for 50M gate ASIC
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A fast discrete placement algorithm for FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Multithreaded memetic algorithm for VLSI placement problem
SEMCCO'11 Proceedings of the Second international conference on Swarm, Evolutionary, and Memetic Computing - Volume Part I
| Hi-index | 0.00 |
Simulated annealing has been shown to be effective in producing good quality results for the standard cell placement problem. Its main drawback is the excessive computation time required, which increases significantly with the problem size. In this paper we present a novel technique for reducing the effective problem size for simulated annealing without compromising the solution quality. We form clusters of cells based on their interconnections, and place them first using conventional simulated annealing. We then break up the clusters, and place the individual cells using another simulated annealing process that does a refinement on the placement. The original problem is thus divided into two subproblems, each requiring much less time. The results with this 2-stage simulated annealing have been superior to those with our conventional simulated annealing implementation, with more significant improvements observed for larger chips. For chips with more than 2500 cells, we have observed a factor of 2 to 3 speed-up in CPU time, together with a 6 to 17% improvement in the estimated wire-length.