A comparison of four two-dimensional gate matrix layout tools

Authors:
M. J. Irwin;R. M. Owens
Affiliations:
Department of Computer Science, The Pennsylvania State University, University Park, PA;Department of Computer Science, The Pennsylvania State University, University Park, PA
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Abstract

A comparison of four layout tools is presented. The layout style is a two-dimensional gate matrix. The first layout tool discussed uses “standard” simulated annealing. Annealing on gate clusters instead of individual gates can be used to improve the layout results. Two different ways of determining good gate clusters for use in the annealing process are compared. The first way uses clusters derived from user specified gate hierarchies, while the second determines clusters based on gate connectivity. The fourth layout tool uses a decomposition scheme based on quadrisection. Layout results for a set of benchmark circuits are presented for each of the tools.