A min-cut placement algorithm for general cell assemblies based on a graph representation
25 years of DAC Papers on Twenty-five years of electronic design automation
A comparison of four two-dimensional gate matrix layout tools
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Computer systems that learn: classification and prediction methods from statistics, neural nets, machine learning, and expert systems
EURO-DAC '92 Proceedings of the conference on European design automation
A layout estimation algorithm for RTL datapaths
DAC '93 Proceedings of the 30th international Design Automation Conference
CMOS VLSI layout synthesis for circuit performance
CMOS VLSI layout synthesis for circuit performance
Policies for the selection of bias in inductive machine learning
Policies for the selection of bias in inductive machine learning
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Introduction to Algorithms: A Creative Approach
Introduction to Algorithms: A Creative Approach
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
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Forward estimates of area and delay facilitate effective decision-making when searching the solution space of digital designs. Current estimation techniques focus on modeling the layout result and fail to deliver timely or accurate estimates. This paper presents a novel approach to deriving these area and delay estimates at the RTL level by modeling the layout tool, rather than the layout result. This approach uses machine learning techniques to capture the relationships between general design features (i.e., topology, connectivity, common input, and common output) and layout concepts (i.e., relative placement). Experiments illustrate the formulation of the training set for machine learning in this domain, and also show how we can derive different tool models. Finally, they show how we can use the resultant model to derive forward estimates of area and delay in real-world designs.