Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Multi-stack optimization for data-path chip (microprocessor) layout
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
EURO-DAC '92 Proceedings of the conference on European design automation
Timing models for high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
On the interaction of functional and timing behaviour of combinational logic circuits
On the interaction of functional and timing behaviour of combinational logic circuits
LAST: a Layout Area and Shape function esTimator for high level applications
EURO-DAC '91 Proceedings of the conference on European design automation
Comprehensive lower bound estimation from behavioral descriptions
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Provably correct high-level timing analysis without path sensitization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A comprehensive estimation technique for high-level synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Domain-specific high-level modeling and synthesis for ATM switch design using VHDL
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Controller and datapath trade-offs in hierarchical RT-level synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient multi-view design model for real-time interactive synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A flexible datapath allocation method for architectural synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modeling layout tools to derive forward estimates of area and delay at the RTL level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
300MHz design methodology of VU for emotion synthesis
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An RTL design-space exploration method for high-level applications
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
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