Benchmarks for cell-based layout systems
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
PLEST: a program for area estimation of VLSI integrated circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Spider, a chip planner for ISL technology
DAC '84 Proceedings of the 21st Design Automation Conference
The genealogical approach to the layout problem
DAC '80 Proceedings of the 17th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A new placement level wirability estimate with measurements
ACM SIGDA Newsletter
A graph theoretic technique to speed up floorplan area optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
EURO-DAC '92 Proceedings of the conference on European design automation
Parallel algorithms for slicing based final placement
EURO-DAC '92 Proceedings of the conference on European design automation
Chip assembly in the PLAYOUT VLSI design system
EURO-DAC '92 Proceedings of the conference on European design automation
A layout estimation algorithm for RTL datapaths
DAC '93 Proceedings of the 30th international Design Automation Conference
Area minimization for hierarchical floorplans
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
An optimal algorithm for area minimization of slicing floorplans
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
TINA: analog placement using enumerative techniques capable of optimizing both area and net length
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
High-level power estimation and the area complexity of Boolean functions
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
Accurate layout area and delay modeling for system level design
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Three-phase chip planning — an improved top-down chip planning strategy
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Fast and accurate estimation of floorplans in logic/high-level synthesis
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Efficient list-approximation techniques for floorplan area minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The effect of pin constraints on layout area
EDTC '95 Proceedings of the 1995 European conference on Design and Test
LAST: a Layout Area and Shape function esTimator for high level applications
EURO-DAC '91 Proceedings of the conference on European design automation
Efficient shape curve construction in floorplan design
EURO-DAC '91 Proceedings of the conference on European design automation
Goal oriented slicing enumeration through shape function clipping
EURO-DAC '91 Proceedings of the conference on European design automation
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
DeFer: deferred decision making enabled fixed-outline floorplanning algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal and heuristic algorithms for solving the binding problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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Area estimation of IC layouts has become an important requirement for early design and top-down chip planning tools. Especially the relation of area and aspect ratio (shape function) is necessary for chip planning. Statistical models have been published with good results for standard cell blocks with near unity aspect ratios. This paper describes a new model for the prediction of shape functions for aspect ratios up to 1:5. The model is based on the shape and connectivity of adjacent cells. It can be used for many different design styles and has been tested for standard cell blocks and for the placement of general cells.Categories: 6, 9