FARM: an efficient feed-through pin assignment algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
LP based cell selection with constraints of timing, area, and power consumption
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Power distribution topology design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Explicit evaluation of short circuit power dissipation for CMOS logic structures
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Transistor reordering rules for power reduction in CMOS gates
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Power reduction by gate sizing with path-oriented slack calculation
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power vs. delay in gate sizing: conflicting objectives?
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Delay optimal partitioning targeting low power VLSI circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimization of post-layout area, delay and power dissipation
Optimization of post-layout area, delay and power dissipation
Constructing lower and upper bounded delay routing trees using linear programming
DAC '96 Proceedings of the 33rd annual Design Automation Conference
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A new feed-through assignment algorithm based on a flow model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Proud: a fast sea-of-gates placement algorithm
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
DAC '82 Proceedings of the 19th Design Automation Conference
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Adaptive low-power address encoding techniques using self-organizing lists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems
Journal of Signal Processing Systems
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This paper presents a survey of layout techniques fordesigning low power digital CMOS circuits. It describes the manyissues facing designers at the physical level of design abstractionand reviews some of the techniques and tools that have been proposedto overcome these difficulties.