An optimum channel-routing algorithm for polycell layouts of integrated circuits
DAC '73 Proceedings of the 10th Design Automation Workshop
LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
A high quality, low cost router for MOS/LSI
DAC '72 Proceedings of the 9th Design Automation Workshop
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
Advanced LILAC - an Automated Layout Generation system for MOS/LSIs
DAC '74 Proceedings of the 11th Design Automation Workshop
Optimal Rotation Problems in Channel Routing
IEEE Transactions on Computers
Provably good routing in graphs: regular arrays
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
Geometrical compaction in one dimension for channel routing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Abstract routing of logic networks for custom module generation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Routing with a scanning window-8Ma unified approach
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On improving channel routability
ACM SIGDA Newsletter
Maximum Alignment of Interchangeable Terminals
IEEE Transactions on Computers
An expert system for channel routing
IEA/AIE '88 Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems - Volume 2
LTX-A system for the directed automatic design of LSI circuits
25 years of DAC Papers on Twenty-five years of electronic design automation
A 2-dimensional placement algorithm for the layout of electrical circuits
25 years of DAC Papers on Twenty-five years of electronic design automation
25 years of DAC Papers on Twenty-five years of electronic design automation
25 years of DAC Papers on Twenty-five years of electronic design automation
Chip layout optimization using critical path weighting
25 years of DAC Papers on Twenty-five years of electronic design automation
Optimal Three-Layer Channel Routing
IEEE Transactions on Computers
An Efficient Channel Routing Algorithm to Yield an Optimal Solution
IEEE Transactions on Computers
General models and algorithms for over-the-cell routing in standard cell design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Using controlled experiments in layout
ACM SIGDA Newsletter
Novel routing schemes for IC layout part I: Two-layer channel routing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Channel density reduction by routing over the cells
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On minimizing the number of L-shaped channels
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A new efficient approach to multilayer channel routing problem
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
New models for four- and five-layer channel routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A pin permutation algorithm for improving over-the-cell channel routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Channel routing of multiterminal nets
Journal of the ACM (JACM)
Nearly optimal algorithms and bounds for multilayer channel routing
Journal of the ACM (JACM)
Routing in a Three-Dimensional Chip
IEEE Transactions on Computers
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
An efficient approach to multi-layer layer assignment with application to via minimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
How to obtain more compactable channel routing solutions
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Improved channel routing by via minimization and shifting
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Crosstalk minimization using wire perturbations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Minimizing channel density by lateral shifting of components
SODA '94 Proceedings of the fifth annual ACM-SIAM symposium on Discrete algorithms
An algorithm for one and half layer channel routing
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
ALPS2: a standard cell layout system for double-layer metal technology
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A routing procedure for mixed array of custom macros and standard cells
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Chameleon: a new multi-layer channel router
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Near-optimal n-layer channel routing
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Manhattan channel routing with good theoretical and practical performance
SODA '90 Proceedings of the first annual ACM-SIAM symposium on Discrete algorithms
A parallel algorithm for finding crossing numbers of channel routing (abstract and references only)
CSC '91 Proceedings of the 19th annual conference on Computer Science
Cost based tradeoff analysis of standard cell designs
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Three-layer bubble-sorting-based nonManhattan channel routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Efficient VLSI Switch-Box Router
IEEE Design & Test
3-Dimensional Single Active Layer Routing
JCDCG '00 Revised Papers from the Japanese Conference on Discrete and Computational Geometry
A gridless multi-layer router for standard cell circuits using CTM cells
EDTC '97 Proceedings of the 1997 European conference on Design and Test
IBM FSD VLSI chip design methodology
DAC '83 Proceedings of the 20th Design Automation Conference
Routing method for VLSI design using irregular cells
DAC '83 Proceedings of the 20th Design Automation Conference
Reducing channel density in standard cell layout
DAC '83 Proceedings of the 20th Design Automation Conference
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Automatic routing of double layer gate arrays using a moving cursor
DAC '83 Proceedings of the 20th Design Automation Conference
An over-cell gate array channel router
DAC '83 Proceedings of the 20th Design Automation Conference
A wire routing scheme for double-layer cell arrays
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing
DAC '81 Proceedings of the 18th Design Automation Conference
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks
DAC '81 Proceedings of the 18th Design Automation Conference
A preprocessor for channel routing
DAC '81 Proceedings of the 18th Design Automation Conference
A dogleg “optimal” channel router with completion enhancements
DAC '81 Proceedings of the 18th Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
SHARPS: A hierarchical layout system for VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
Methods for hierarchical automatic layout of custom LSI circuit masks
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Efficient placement and routing techniques for master slice LSI
DAC '80 Proceedings of the 17th Design Automation Conference
The genealogical approach to the layout problem
DAC '80 Proceedings of the 17th Design Automation Conference
LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
A 2-dimensional placement algorithm for the layout of electrical circuits.
DAC '76 Proceedings of the 13th Design Automation Conference
PRO - an automatic string placement program for polycell layout
DAC '76 Proceedings of the 13th Design Automation Conference
An approximation algorithm for manhattan routing
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
A new two-dimensional routing algorithm
DAC '82 Proceedings of the 19th Design Automation Conference
A minimum-impact routing algorithm
DAC '82 Proceedings of the 19th Design Automation Conference
The 1-2-3 routing algorithm or the single channel 2-step router on 3 interconnection layers
DAC '82 Proceedings of the 19th Design Automation Conference
A consideration of the number of horizontal grids used in the routing of a masterslice layout
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
SAGA: An Experimental Silicon Assembler
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Two-dimensional channel routing and channel intersection problems
DAC '82 Proceedings of the 19th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
Hierarchical top-down layout design method for VLSI chip
DAC '82 Proceedings of the 19th Design Automation Conference
CGALA-a multi technology Gate Array Layout system
DAC '82 Proceedings of the 19th Design Automation Conference
On routing for custom integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
On routing two-point nets across a channel
DAC '82 Proceedings of the 19th Design Automation Conference
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI
DAC '79 Proceedings of the 16th Design Automation Conference
The minimum width routing of A 2-row 2-layer polycell-layout
DAC '79 Proceedings of the 16th Design Automation Conference
MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks
DAC '79 Proceedings of the 16th Design Automation Conference
A general graph theoretic framework for multi-layer channel routing
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Computing area and wire length efficient routes for channels
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Channel routing with non-terminal doglegs
EURO-DAC '90 Proceedings of the conference on European design automation
An evolutionary constraint satisfaction solution for over the cell channel routing
Integration, the VLSI Journal
An interactive system for VLSI chip physical design
IBM Journal of Research and Development
QCA channel routing with wire crossing minimization
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Equidistance routing in high-speed VLSI layout design
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Routing vertex disjoint steiner-trees in a cubic grid and connections to VLSI
Discrete Applied Mathematics
A computer-aided VLSI layout system
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Algorithms for permutation channel routing
Integration, the VLSI Journal
Equidistance routing in high-speed VLSI layout design
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Paper: An application of neural networks on channel routing problem
Parallel Computing
Algorithms and theory of computation handbook
On old and new routing problems
Proceedings of the 2011 international symposium on Physical design
On pioneering nanometer-era routing problems
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
| Hi-index | 0.01 |
This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were typical.