An algorithm for one and half layer channel routing

Authors:
J. N. Song;Y. K. Chen
Affiliations:
Department of Electrical Engineering, Tsinghua University, Beijing, China;Department of Electrical Engineering, Tsinghua University, Beijing, China
Venue:
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Year:
1985

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Abstract

Channel routing is one of the key problems in the automatic layout design of LSI chips. This paper presents an efficient routing algorithm for one-and-half layer channel model which is based on single layer metal mask and fixed polysilicon crossunders in CMOS gate array. The algorithm makes parallel horizontal routing in each zone by means of ordering and prediction. The nets contend for crossunders in a greedy approach. This results in higher probability of routing success and less crossunders occupied (equally less via holes). Furthermore, by inserting interactive information at the same time of execution if necessary, the router provides more chances of 100% routing success.