An intelligent compiler subsystem for a silicon compiler

Authors:
D. L. Johannsen;S. K. Tsubota;K McElvain
Affiliations:
-;-;-
Venue:
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Year:
1987

Citing 6
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Abstract

This paper presents a module generator which automatically generates and optimizes circuitry to satisfy constraints of speed, area and power. The user has complete control over the clock timing driving the circuitry and the area, width, or height of the resulting module. Unlike other programs that have been optimized for area and speed, this program supports more degrees of freedom and a broad range of circuit constructs, permitting a complete integrated circuit to be designed to meet the overall IC project objectives.