Delay and power optimization in VLSI circuits

Authors:
Lance A. Glasser;Lennox P.J. Hoyte
Affiliations:
Electrical Engineering and Computer Science Department and the Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, Massachusetts;Electrical Engineering and Computer Science Department and the Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, Massachusetts
Venue:
DAC '84 Proceedings of the 21st Design Automation Conference
Year:
1984

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Abstract

The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macromodels are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.