A new algorithm for transistor sizing in CMOS circuits

Authors:
C. H. Allen Wu;Nels Vander Zanden;Daniel Gajski
Affiliations:
University of California at Irvine, Irvine, CA.;University of California at Irvine, Irvine, CA.;University of California at Irvine, Irvine, CA.
Venue:
EURO-DAC '90 Proceedings of the conference on European design automation
Year:
1990

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Abstract

This paper describes a new algorithm for automatic transistor sizing in CMOS circuits. The algorithm consists of three phases: critical path analysis, transistor sizing and transistor desizing. This approach is different from conventional sizing methods that optimize a given design locally, using one or several paths at a time. Our algorithm reduces the delays of all paths in a given design simultaneously. Using our transistor desizing approach, the minimal transistor areas can be achieved to meet a set of timing requirements. Furthermore, by tuning NFET and PFET transistor sizes separately, this algorithm has control over rise and fall time delays of a gate depending on the input trigger signal. Experimental results show that this algorithm can improve the delay in approximately linear time.