Introduction to VLSI Systems
A multiple media delay simulator for MOS LSI circuits
DAC '83 Proceedings of the 20th Design Automation Conference
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '83 Proceedings of the 20th Design Automation Conference
Architecture of a VLSI instruction cache for a RISC
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
Relax: A new circuit for large scale MOS integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
Timing Models for MOS Circuits
Timing Models for MOS Circuits
Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Worst-case delay estimation of transistor groups
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
ADAPTS: A digital transient simulation strategy for integrated circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing verification on a 1.2M-device full-custom CMOS design
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Elmore delay as bound for RC trees with generalized input signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Power estimation tool for sub-micron CMOS VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Electrical optimization of PLAs
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
SIMMOS: a multiple-delay switch-level simulator
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An effective delay analysis system for a large scale computer design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Plug-in timing models for an abstract timing verifier
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Hierarchical VLSI design systems based on attribute grammars
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Efficient simulation of interconnect and mixed analog-digital circuits in ACES
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Path runner: an accurate and fast timing analyser
EURO-DAC '90 Proceedings of the conference on European design automation
A new algorithm for transistor sizing in CMOS circuits
EURO-DAC '90 Proceedings of the conference on European design automation
TAS: an accurate timing analyser for CMOS VLSI
EURO-DAC '91 Proceedings of the conference on European design automation
A hierarchical approach to timing verification in CMOS VLSI design
EURO-DAC '91 Proceedings of the conference on European design automation
RESTA: a robust and extendable symbolic timing analysis tool
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
General transistor-level methodology on VLSI low-power design
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Area and delay trade-offs in the circuit and architecture design of FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Automated transistor sizing for FPGA architecture exploration
Proceedings of the 45th annual Design Automation Conference
Transistor sizing for large combinational digital CMOS circuits
Integration, the VLSI Journal
Exploring area and delay tradeoffs in FPGAs with architecture and automated transistor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
This paper presents fast, simple, and relatively accurate delay models for large digital MOS circuits. Delay modeling is organized around chains of switches and nodes called stages, instead of logic gates. The use of stages permits both logic gates and pass transistor arrays to be handled in a uniform fashion. Three delay models are presented, ranging from an RC model that typically errs by 25% to a slope-based model whose delay estimates are typically within 10% of SPICE's estimates. The slope model is parameterized in terms of the ratio between the slopes of a stage's input and output waveforms. All the models have been implemented in the Crystal timing analyzer. They are evaluated by comparing their delay estimates to SPICE, using a dozen critical paths from two VLSI designs.