A hierarchical approach to timing verification in CMOS VLSI design

Authors:
H. G. Yang;D. M. Holburn
Affiliations:
Cambridge University, Cambridge, England;Cambridge University, Cambridge, England
Venue:
EURO-DAC '91 Proceedings of the conference on European design automation
Year:
1991

Citing 8
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Abstract

This paper describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded delay values for large hierarchical systems can be deduced using bounded delays determined for their constituent cells. Finally, we discuss the impact on design strategy of the hierarchical delay model presented in this paper.