LSS: a system for production logic synthesis
IBM Journal of Research and Development
Is redundancy necessary to reduce delay
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The exact solution of timing verification
EURO-DAC '92 Proceedings of the conference on European design automation
Gate-level timing verification using waveform narrowing
EURO-DAC '94 Proceedings of the conference on European design automation
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
False loops through resource sharing
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Timing-safe false path removal for combinational modules
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Propagation of last-transition-time constraints in gate-level timing analysis
Proceedings of the conference on Design, automation and test in Europe
Logic Synthesis and Verification
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
SLOCOP-II: a versatile timing verification system for MOSVLSI
EURO-DAC '90 Proceedings of the conference on European design automation
A hierarchical approach to timing verification in CMOS VLSI design
EURO-DAC '91 Proceedings of the conference on European design automation
Certified timing verification and the transition delay of a logic circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 14.98 |
The usual block-oriented timing analysis for logic circuits does not take into account functional relations between signals. If functional relations are taken into consideration, it could be found that a long path is never activated. This results in more accurate delays. A comparison is made of three arrival time functions, A, B, and R. A is the arrival time as given by exhaustive simulation; B is the arrival time as calculated by a usual block-oriented algorithm; and R is the arrival time, that does functional analysis. It is shown that B contained in R contained in A. The first relation means that R is never more conservative than B and whenever the containment is proper, R is an improvement over B. The second relation means that R is correct in the sense that it will never assert a signal to be valid when it is not valid according to the ideal A. Experimental results showing how often R is an improvement over B are presented.