Logic Design of Digital Systems
Logic Design of Digital Systems
DAC '83 Proceedings of the 20th Design Automation Conference
Development and application of a designer oriented cyclic simulator
DAC '76 Proceedings of the 13th Design Automation Conference
Bristle Blocks: A silicon compiler
DAC '79 Proceedings of the 16th Design Automation Conference
IBM Journal of Research and Development
Delay optimization of combinational static CMOS logic
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
TRIP: an automated technology mapping system
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Function search from behavioral description of a digital system
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Timing Analysis Using Functional Analysis
IEEE Transactions on Computers
Anatomy of a hardware compiler
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
DAGON: Technology binding and local optimization by DAG matching
25 years of DAC Papers on Twenty-five years of electronic design automation
A Note on Detecting Sneak Paths in Transistor Networks
IEEE Transactions on Computers
The MICON system for computer design
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing optimization for multi-level combinational networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Timing optimization on mapped circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A resynthesis approach for network optimization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Data-path synthesis using path analysis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Optimization of primitive gate networks using multiple output two-level minimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Control optimization in high-level synthesis using behavioral don't cares
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level synthesis in an industrial environment
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Speeding up technology-independent timing optimization by network partitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing analysis in high-level synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Technology adaption in logic synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Incremental logic synthesis through gate logic structure identification
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
Technology-based transformations
Logic Synthesis and Verification
The V Compiler: Automatic Hardware Design
IEEE Design & Test
A Model-Based Expert System for Digital System Design
IEEE Design & Test
The Micon System for Computer Design
IEEE Micro
Resynthesis of multi-level circuits under tight constraints using symbolic optimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Improved technology mapping using a new approach to Boolean matching
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Design and test of the PowerPC 603 microprocessor
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Rapid Gate Matching with Don't Cares
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Technology mapping using boolean matching and don't care sets
EURO-DAC '90 Proceedings of the conference on European design automation
A new synthesis technique for multilevel combinational circuits
EURO-DAC '90 Proceedings of the conference on European design automation
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IBM Journal of Research and Development
Data structures and algorithms for simplifying reversible circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Detecting Sneak Paths in Transistor Networks
IEEE Transactions on Computers
iCOACH: A circuit optimization aid for CMOS high-performance circuits
Integration, the VLSI Journal
Integration letter: Information flow in VLSI design
Integration, the VLSI Journal
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For some time we have been exploring methods of transforming functional specifications into hardware implementations that are suitable for production. The complexity of this task and the potential value have continued to grow with the increasing complexity of processor design and the mounting pressure to shorten machine design times. This paper describes the evolution of the Logic Synthesis System from an experimental tool to a production system for the synthesis of masterslice chip implementations. The system was used by one project in IBM Poughkeepsie to produce 90 percent of its more than one hundred chip parts. The primary reasons for this success are the use of local transformations to simplify logic representations at several levels of abstraction, and a highly cooperative effort between logic designers and synthesis system designers to understand the logic design process practiced in Poughkeepsie and to incorporate this knowledge into the synthesis system.