Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Technology adaption in logic synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic Design and Switching Theory
Logic Design and Switching Theory
LSS: a system for production logic synthesis
IBM Journal of Research and Development
A technology mapping method based on perfect and semi-perfect matchings
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A resynthesis approach for network optimization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Logic optimization of MOS networks
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Efficient sum-to-one subsets algorithm for logic optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Timing optimization by gate resizing and critical path identification
DAC '93 Proceedings of the 30th international Design Automation Conference
Logic clause analysis for delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Timing optimization by an improved redundancy addition and removal technique
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Speeding up technology-independent timing optimization by network partitioning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance-driven integration of retiming and resynthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dominator-based partitioning for delay optimization
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Timing-driven optimization using lookahead logic circuits
Proceedings of the 46th Annual Design Automation Conference
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This paper presents a timing optimization algorithm SDLR (acronym of SYLON-DREAM Level-Reduction), which is used in the SYLON-DREAM logic synthesizer for speeding up combinational multi-level networks. In SDLR, gates on critical paths are identified and their level numbers counted from the inputs of the network are maximally reduced by a level-reduction procedure. Gates which are not on the critical paths are processed by an area reduction procedure to reduce network area without increasing its maximum depth. SDLR uses the concept of permissible functions in both level and area reduction procedures, and it can directly process networks consisting of simple gates or negative gates (i.e., MOS cells). Experimental results obtained for benchmark functions show that SDLR is an effective algorithm which can reduce network delay with no or minimal area increase.