Logic Design and Switching Theory
Logic Design and Switching Theory
Timing optimization for multi-level combinational networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Efficient implementation of a BDD package
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Boolean resubstitution with permissible functions and binary decision diagrams
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A resynthesis approach for network optimization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Logic optimization of MOS networks
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Incremental techniques for the identification of statically sensitizable critical paths
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Efficient sum-to-one subsets algorithm for logic optimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Recurrence equations and the optimization of synchronous logic circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Boolean matching in logic synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Maximal reduction of lookup-table based FPGAs
EURO-DAC '92 Proceedings of the conference on European design automation
Optimization of combinational logic circuits based on compatible gates
DAC '93 Proceedings of the 30th international Design Automation Conference
Perturb and simplify: multi-level boolean network optimizer
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A redesign technique for combinational circuits based on gate reconnections
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Random generation of test instances for logic optimizers
DAC '94 Proceedings of the 31st annual Design Automation Conference
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A partitioning-based logic optimization method for large scale circuits with Boolean matrix
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Multi-level logic minimization based on multi-signal implications
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient algorithm for local don't care sets calculation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic clause analysis for delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
LOT: logic optimization with testability—new transformations using recursive learning
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Multi-level logic optimization of FSM networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Design of a logic synthesis system (tutorial)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Reducing power dissipation after technology mapping by structural transformations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A new method to express functional permissibilities for LUT based FPGAs and its applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Fast Boolean optimization by rewiring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Polarized observability don't cares
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Gate-level synthesis for low-power using new transformations
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
The maximum set of permissible behaviors for FSM networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Maximum projections of don't care conditions in a Boolean network
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Technology-dependent transformations for low-power synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Sequential optimisation without state space exploration
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Logic transformation for low power synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Behavioral synthesis of combinational logic using spectral-based heuristics
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power and delay reduction via simultaneous logic and placement optimization in FPGAs
DATE '00 Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic transformation for low-power synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multi-level logic optimization
Logic Synthesis and Verification
Logic Synthesis and Verification
Compatible observability don't cares revisited
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On the properties of the input pattern fault model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low power design and its testability
ATS '95 Proceedings of the 4th Asian Test Symposium
Sequential Permissible Functions and their Application to Circuit Optimization
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Random Benchmark Circuits with Controlled Attributes
EDTC '97 Proceedings of the 1997 European conference on Design and Test
The input pattern fault model and its application
EDTC '97 Proceedings of the 1997 European conference on Design and Test
LUT-based FPGA Technology Mapping using Permissible Functions
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Transduction method for design of logic cell structure
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A transduction-based framework to synthesize RSFQ circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Logic optimization for asynchronous speed independent controllers using transduction method
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Applicability of feed-forward and recurrent neural networks to Boolean function complexity modeling
Expert Systems with Applications: An International Journal
Scalable don't-care-based logic optimization and resynthesis
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Logic synthesis and circuit customization using extensive external don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic design error diagnosis and correction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable don't-care-based logic optimization and resynthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 14.98 |
Based on the new concept of permissible functions, a heuristic procedure to design logic networks with as few gates as possible, without guaranteeing the minimality of designed networks, is developed. This procedure, which is drastically different from conventional logic-design procedures, is called the transduction method, because an initial network designed by any conventionally known logic-design method is first transformed into a different network configuration and then reduced to a simpler network by calculating permissible functions at the outputs of gates and connections throughout the network.