The Transduction Method-Design of Logic Networks Based on Permissible Functions
IEEE Transactions on Computers
Multi-level logic simplification using don't cares and filters
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A resynthesis approach for network optimization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Boolean matching in logic synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
An efficient algorithm for local don't care sets calculation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An estimation technique to guide low power resynthesis algorithms
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Techniques for verifying superscalar microprocessors
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A new method to express functional permissibilities for LUT based FPGAs and its applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Logic synthesis using power-sensitive don't care sets
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Maximum projections of don't care conditions in a Boolean network
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Engineering change for power optimization using global sensitivity and synthesis flexibility
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Performance driven resynthesis by exploiting retiming-induced state register equivalence
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Logic Synthesis and Verification
Compatible observability don't cares revisited
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Simplification of non-deterministic multi-valued networks
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Identifying Redundant Wire Replacements for Synthesis and Verification
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Identifying Redundant Gate Replacements in Verification by Error Modeling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
A robust algorithm for approximate compatible observability don't care (CODC) computation
Proceedings of the 41st annual Design Automation Conference
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Don't cares in logic minimization of extended finite state machines
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Comparison of schemes for encoding unobservability in translation to SAT
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Minimizing FPGA Reconfiguration Data at Logic Level
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
SAT sweeping with local observability don't-cares
Proceedings of the 43rd annual Design Automation Conference
DDBDD: delay-driven BDD synthesis for FPGAs
Proceedings of the 44th annual Design Automation Conference
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Robust window-based multi-node technology-independent logic minimization
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Logic synthesis and circuit customization using extensive external don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications
Proceedings of the 47th Design Automation Conference
Sequential logic synthesis using symbolic bi-decomposition
Proceedings of the Conference on Design, Automation and Test in Europe
SALSA: systematic logic synthesis of approximate circuits
Proceedings of the 49th Annual Design Automation Conference
Generalized SAT-sweeping for post-mapping optimization
Proceedings of the 49th Annual Design Automation Conference
| Hi-index | 0.00 |
We give an algorithm for computing subsets of observability don't cares at the nodes of a multi-level Boolean network. These subsets are based on an extension of the methods introduced in [4] for computing compatible sets of permissible functions (CSPF's) at the nodes of networks composed of NOR gates. The extensions presented are in four directions; an arbitrary logic function is allowed at any node, the don't cares are expressed in terms of both primary inputs and intermediate variables, a new ordering scheme is used, and maximal CSPF's are computed. These ideas are incorporated in an algorithm designed to take full advantage of the power of two-level minimization in multi-level logic synthesis systems. This has been implemented in MIS-II and we present results that demonstrate the effectiveness of these techniques.