The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Optimizing designs containing black boxes
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Making complex timing relationships readable: Presburger formula simplicication using don't cares
DAC '98 Proceedings of the 35th annual Design Automation Conference
On speeding up extended finite state machines using catalyst circuitry
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Software synthesis from synchronous specifications using logic simulation techniques
Proceedings of the 39th annual Design Automation Conference
Don't cares and multi-valued logic network minimization
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Design Verfication and Reachability Analysis Using Algebraic Manipulation
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
A Comparison of Presburger Engines for EFSM Reachability
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Symbolic Model Checking of Infinite State Systems Using Presburger Arithmetic
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Synthesis of software programs for embedded control applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Extended Finite State Machines (EFSMs) have been proposed to model control oriented systems. A version of this, with the data portion modeled by Presburger arithmetic, has been used in formal verification and test pattern generation. This paper proposes a general logic minimization scheme using don't care derived from both control and data path. It consists of methods to transfer don't cares through the data path and to generate logic don't cares from the data path using quantifier-free Presburger inequalities. Potential applications are discussed and preliminary results validate the scheme on reasonable examples.