A practical algorithm for exact array dependence analysis
Communications of the ACM
An approach to symbolic timing verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Interface timing verification with application to synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimization of linear max-plus systems with application to timing analysis
Optimization of linear max-plus systems with application to timing analysis
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
An Exact Method for Analysis of Value-based Array Data Dependences
Proceedings of the 6th International Workshop on Languages and Compilers for Parallel Computing
Finding Legal Reordering Transformations Using Mappings
LCPC '94 Proceedings of the 7th International Workshop on Languages and Compilers for Parallel Computing
Exact analysis of the cache behavior of nested loops
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
The future of logic synthesis and verification
Logic Synthesis and Verification
Symbolic Time Separation of Events
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Don't cares in logic minimization of extended finite state machines
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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Solutions to timing relationship analysis problems are often reported using symbolic variables and inequalities which specify linear relationships between the variables. Complex relationships can be expressed using Presburger formulas which allow Boolean relations to be specified between the inequalities. This paper develops and applies a highly effective simplification approach for Presburger formulas based on logic minimization techniques.