Timing verification using HDTV
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A practical algorithm for exact array dependence analysis
Communications of the ACM
An approach to symbolic timing verification
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Interface timing verification with application to synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimization of linear max-plus systems with application to timing analysis
Optimization of linear max-plus systems with application to timing analysis
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
An Exact Method for Analysis of Value-based Array Data Dependences
Proceedings of the 6th International Workshop on Languages and Compilers for Parallel Computing
Temporal Analysis of Time Bounded Digital Systems
CHARME '93 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Integrating Behavior and Timing in Executable Specifications
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Interface Timing Verification with Delay Correlation Using Constraint Logic Programming
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A new interface specification methodology and its application to transducer synthesis
A new interface specification methodology and its application to transducer synthesis
Making complex timing relationships readable: Presburger formula simplicication using don't cares
DAC '98 Proceedings of the 35th annual Design Automation Conference
Exact analysis of the cache behavior of nested loops
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Model Checking Synchronous Timing Diagrams
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Time Separation of Events
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification of timed circuits with symbolic delays
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Reasoning about synchronization in GALS systems
Formal Methods in System Design
Time Separation of Events: An Inverse Method
Electronic Notes in Theoretical Computer Science (ENTCS)
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Cuts from Proofs: A Complete and Practical Technique for Solving Linear Inequalities over Integers
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Out of order quantifier elimination for Standard Quantified Linear Programs
Journal of Symbolic Computation
Cuts from proofs: a complete and practical technique for solving linear inequalities over integers
Formal Methods in System Design
A scalable method for solving satisfiability of integer linear arithmetic logic
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Testing deadlock-freeness in real-time systems: a formal approach
FATES'04 Proceedings of the 4th international conference on Formal Approaches to Software Testing
From propositional satisfiability to satisfiability modulo theories
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
A progressive simplifier for satisfiability modulo theories
SAT'06 Proceedings of the 9th international conference on Theory and Applications of Satisfiability Testing
Verification of Concurrent Systems with Parametric Delays Using Octahedra
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
A simple and flexible timing constraint logic
ISoLA'12 Proceedings of the 5th international conference on Leveraging Applications of Formal Methods, Verification and Validation: applications and case studies - Volume Part II
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We present a novel set of tools for performing symbolic timing verificationof timing diagrams. The tools are multi-purpose with usesin verification, derivation of synthesis constraints, and design evaluation.Our methodology is based on using techniques for manipulatingPresburger formulas. We demonstrate using several interestingexamples that the method is efficient in practice and should beconsidered for inclusion in commercial tools.