Automatic production of controller specifications from control and timing behavioral descriptions
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
ATV: an abstract timing verifier
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Algorithms for timing requirement analysis and generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Plug-in timing models for an abstract timing verifier
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Maintaining knowledge about temporal intervals
Communications of the ACM
An Expert System to Automate Timing Design
IEEE Design & Test
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Abstract Timing Verification for Synchronous Digital System
Abstract Timing Verification for Synchronous Digital System
A New Interface Specification Methodology and
A New Interface Specification Methodology and
CLOVER: a timing constraints verification system
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Simulation of digital circuits in the presence of uncertainty
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Automated multi-cycle symbolic timing verification of microprocessor-based designs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Symbolic timing verification of timing diagrams using Presburger formulas
DAC '97 Proceedings of the 34th annual Design Automation Conference
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
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In this paper, we provide an overview of a system designed for verifying the consistency of timing specifications for digital circuits. The utility of the system comes from the need to verify that existing digital components will interact correctly when placed together in a system. The system can also be used in the case of verifying specifications of unimplemented components.