CommonLoops: merging Lisp and object-oriented programming
OOPLSA '86 Conference proceedings on Object-oriented programming systems, languages and applications
Common LISP: the language
SCAT—a new statistical timing verifier in a silicon compiler system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Plug-in timing models for an abstract timing verifier
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Abstract timing verification for synchronous digital systems
Abstract timing verification for synchronous digital systems
Timing analysis in a logic synthesis environment
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Timing verification using HDTV
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Timing verification on a 1.2M-device full-custom CMOS design
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A verification technique for gated clock
DAC '93 Proceedings of the 30th international Design Automation Conference
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A case against event-driven simulation for digital system design
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Static timing analysis taking crosstallk into account
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Clock independent timing verification of level-sensitive latches
EURO-DAC '91 Proceedings of the conference on European design automation
Specification of timing constraints for controller synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
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We discuss implementation and extensions of the Abstract Timing Verifier proposed in [WaS86], in particular, several new operations and a new algorithm for analyzing critical paths that extend through transparent latches and stretch over multiple machine cycles. By placing events in different reference frames that can be translated relative to one another, the program can be used either to check a design for timing errors when the clock schedule is fixed and known, or to derive spacing constraints between clock edges when only the relative ordering of the clock edges is known. The algorithms are designed to operate on a wide variety of representations of time and delay.