Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Timing analysis in a logic synthesis environment
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Automatic determination of optimal clocking parameters in synchronous MOS VLSI circuits
Proceedings of the fifth MIT conference on Advanced research in VLSI
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ATV: an abstract timing verifier
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Resynthesis of multi-phase pipelines
DAC '93 Proceedings of the 30th international Design Automation Conference
A timing analysis algorithm for circuits with level-sensitive latches
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Clock skew optimization for ground bounce control
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clock skew scheduling for improved reliability via quadratic programming
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip
Discrete Applied Mathematics
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Clock schedule verification under process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient incremental clock latency scheduling for large circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
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