Data structures and network algorithms
Data structures and network algorithms
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Data Structures and Algorithms
Data Structures and Algorithms
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
An algorithm for incremental timing analysis
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Static statistical timing analysis for latch-based pipeline designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing modeling of latch-controlled sub-systems
Integration, the VLSI Journal
Latch modeling for statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Intel® atom™ processor core made FPGA-synthesizable
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the modified shortest and longest path method. The computational complexity of our algorithm is generally better than that of known algorithms in the literature. The implementation (CYCLOPSS) has been applied to an industrial chip to verify the clock schedules.