Timing modeling of latch-controlled sub-systems

Authors:
Kyung Tae Do;Young Hwan Kim;Haeng Seon Son
Affiliations:
Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, San 31, Hyoja-dong, Pohang, Kyungbuk 790-784, Republic of Korea;Department of Electronic and Electrical Engineering, Pohang University of Science and Technology, San 31, Hyoja-dong, Pohang, Kyungbuk 790-784, Republic of Korea;SoC Research Center, Korea Electronics Technology Institute, 68 Yatap-dong, Bundang-gu, Seongnam, Gyeonggi 468-816, Republic of Korea
Venue:
Integration, the VLSI Journal
Year:
2007

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Abstract

We present a new timing model for latch-controlled sub-systems, referred to as the advanced black box model. The proposed model considers the transparency characteristics of latches in modeling and uses only the constraints on input signals and the characteristics of output departure time to represent the timing characteristics of the latch-controlled sub-system. Thus, it can be used for the efficient timing verification of the IP-based SoC design without re-verifying the internal timings of pre-verified Intellectual Properties (IPs) at the lower level. We also present an efficient algorithm to characterize the proposed model, which enables us to perform the timing characterization and verification of the given system simultaneously. The worst-case complexity of the entire characterization process is O(PxN^2), where P and N are the numbers of primary inputs and latches in the system.