Critical paths in circuits with level-sensitive latches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing macro-modeling of IP blocks with crosstalk
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing modeling of latch-controlled sub-systems
Integration, the VLSI Journal
A hierarchical approach towards system level static timing verification of SoCs
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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We have developed a new timing abstraction model for digital circuit blocks that is stimulus independent, port based, supports designs with level triggered latches, and can be input into commercial STA (Static Timing Analysis) tools. The model is based on an extension of the concept of latch transparency to circuit block transparency introduced in this paper. It was implemented, tested and is being used in conjunction with transistor level STA for microprocessor designs with tens of millions of transistors. The STA simulation times are significantly shorter than with gray box timing models, which can decrease the overall chip timing verification time. The model can also be used in the intellectual property encapsulation domain.