Introduction to algorithms
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Efficient implementation of retiming
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automated timing model generation
Proceedings of the 39th annual Design Automation Conference
Timing model extraction of hierarchical blocks by graph reduction
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Physical planning with retiming
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multilevel global placement with retiming
Proceedings of the 40th annual Design Automation Conference
Optimal clock period clustering for sequential circuits with retiming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing large multiphase level-clocked circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire Retiming for System-on-Chip by Fixpoint Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Performance-driven register insertion in placement
Proceedings of the 2004 international symposium on Physical design
A method for correcting the functionality of a wire-pipelined circuit
Proceedings of the 41st annual Design Automation Conference
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Exploiting level sensitive latches in wire pipelining
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimal wire retiming without binary search
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Spec-based flip-flop and latch repeater planning
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Processing Rate Optimization by Sequential System Floorplanning
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Fast timing closure by interconnect criticality driven delay relaxation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A general model for performance optimization of sequential systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Practical asynchronous interconnect network design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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At the integration scale of System-On-Chips (SOCs), the conflicts between communication and computation will become prominent even on a chip. A big fraction of system time willshift from computation to communication. In synchronoussystems, a large amount of communication time is spent onmultiple-clock period wires. In this paper, we explore retimingto pipeline long interconnect wires in SOC designs. Behaviorally,it means that both computation and communicationare rescheduled for parallelism. The retiming is applied to anetlist of macro-blocks, where the internal structures may notbe changed and ip- ops may not be able to be inserted onsome wire segments. This problem is different from that on agate level netlist and is formulated as a wire retiming problem.Theoretical treatment and a polynomial time algorithmare presented in the paper. Experimental results showed thebenefits and effectiveness of our approach.