Introduction to algorithms
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A simultaneous routing tree construction and fanout optimization algorithm
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A fast algorithm for context-aware buffer insertion
Proceedings of the 37th Annual Design Automation Conference
Maze routing with buffer insertion and wiresizing
Proceedings of the 37th Annual Design Automation Conference
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
Meeting delay constraints in DSM by minimal repeater insertion
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A fast algorithm for context-aware buffer insertion
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Buffer insertion with adaptive blockage avoidance
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 2002 international symposium on Physical design
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
Proceedings of the 2002 international symposium on Physical design
S-Tree: a technique for buffered routing tree synthesis
Proceedings of the 39th annual Design Automation Conference
Logical and physical design: a flow perspective
Logic Synthesis and Verification
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Porosity aware buffered steiner tree construction
Proceedings of the 2003 international symposium on Physical design
Buffered Routing Tree Construction Under Buffer Placement Blockages
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Wire Retiming for System-on-Chip by Fixpoint Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Fast and flexible buffer trees that navigate the physical layout environment
Proceedings of the 41st annual Design Automation Conference
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A place and route aware buffered Steiner tree construction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Tradeoff routing resource, runtime and quality in buffered routing
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Optimal wire retiming without binary search
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Concurrent flip-flop and buffer insertion with adaptive blockage avoidance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient algorithms for buffer insertion in general circuits based on network flow
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
Proceedings of the 46th Annual Design Automation Conference
A new clock network synthesizer for modern VLSI designs
Integration, the VLSI Journal
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