DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computational geometry: algorithms and applications
Computational geometry: algorithms and applications
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
A simultaneous routing tree construction and fanout optimization algorithm
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A fast algorithm for context-aware buffer insertion
Proceedings of the 37th Annual Design Automation Conference
Maze routing with buffer insertion and wiresizing
Proceedings of the 37th Annual Design Automation Conference
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffered Steiner trees for difficult instances
Proceedings of the 2001 international symposium on Physical design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Simultaneous Routing and Buffer Insertion for High Performance Interconnect
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Steiner tree optimization for buffers, blockages, and bays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Porosity aware buffered steiner tree construction
Proceedings of the 2003 international symposium on Physical design
A place and route aware buffered Steiner tree construction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Accurate estimation of global buffer delay within a floorplan
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Algorithm engineering: bridging the gap between algorithm theory and practice
Algorithm engineering: bridging the gap between algorithm theory and practice
Depth controlled symmetric function fanin tree restructure
Proceedings of the International Conference on Computer-Aided Design
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Buffer insertion is a fundamental technology for VLSI interconnect optimization. Several existing buffer insertion algorithms have evolved from van Ginneken's classic algorithm. In this work, we extend van Ginneken's algorithm to handle blockages in the layout. Given a Steiner tree containing a Steiner point that overlaps a blockage, a local adjustment is made to the tree topology that enables additional buffer insertion candidates to be considered. This adjustment is adaptive to the demand on buffer insertion and is incurred only when it facilitates the maximal slack solution. This approach can be combined with any performance-driven Steiner tree construction. The overall time complexity has linear dependence on the number of blockages and quadratic dependence on the number of potential buffer locations. Experiments on several large nets confirm that high-quality solutions can be obtained through this technique with little CPU cost.