Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A fast algorithm for context-aware buffer insertion
Proceedings of the 37th Annual Design Automation Conference
Maze routing with buffer insertion and wiresizing
Proceedings of the 37th Annual Design Automation Conference
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Buffer insertion with adaptive blockage avoidance
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 2002 international symposium on Physical design
S-Tree: a technique for buffered routing tree synthesis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Simultaneous Routing and Buffer Insertion for High Performance Interconnect
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Steiner tree optimization for buffers, blockages, and bays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2004 international symposium on Physical design
Fast and flexible buffer trees that navigate the physical layout environment
Proceedings of the 41st annual Design Automation Conference
Modeling repeaters explicitly within analytical placement
Proceedings of the 41st annual Design Automation Conference
A place and route aware buffered Steiner tree construction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient generation of short and fast repeater tree topologies
Proceedings of the 2006 international symposium on Physical design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis system. Modern designs may contain large blocks which severely constrain the buffer locations. Even when there may appear to be space for buffers in the alleys between large blocks, these regions are often densely packed or may needed later to fix critical paths. Therefore, within physical synthesis, a buffer insertion scheme needs to be aware of the porosity of the existing layout to be able to decide when to insert buffers in dense regions to achieve critical performance improvement and when to utilize the sparser regions of the chip.This work addresses the problem of finding porosity-aware buffering solutions by constructing a "smart Steiner tree" to pass to van Ginneken's topology based algorithm. This flow allows one to fully integrate the algorithm into a physical synthesis system without paying an exorbitant runtime penalty. We show that significant improvements on timing closure are obtained when this approach is integrated into a physical synthesis system.