Buffer insertion with adaptive blockage avoidance
Proceedings of the 2002 international symposium on Physical design
Porosity aware buffered steiner tree construction
Proceedings of the 2003 international symposium on Physical design
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Probabilistic Analysis of Rectilinear Steiner Trees
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Buffered Routing Tree Construction Under Buffer Placement Blockages
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A place and route aware buffered Steiner tree construction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
Proceedings of the 42nd annual Design Automation Conference
Efficient generation of short and fast repeater tree topologies
Proceedings of the 2006 international symposium on Physical design
Minimizing clock latency range in robust clock tree synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Embedding repeaters in silicon IPs for cross-IP interconnections
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.03 |
Timing optimization is a critical component of deep submicrometer design and buffer insertion is an essential technique for achieving timing closure. This work studies buffer insertion under the constraint that the buffers either: (1) avoid blockages or (2) are contained within preassigned buffer bay regions. We propose a general Steiner-tree formulation to drive this application and present a maze-routing-based heuristic that either avoids blockages or finds buffer bays. We show that the combination of our Steiner-tree optimization with leading-edge buffer-insertion techniques leads to effective solutions on industry designs