Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Maze routing with buffer insertion and wiresizing
Proceedings of the 37th Annual Design Automation Conference
An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Timing closure based on physical hierarchy
Proceedings of the 2002 international symposium on Physical design
Simultaneous routing and buffer insertion with restrictions on buffer locations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Steiner tree optimization for buffers, blockages, and bays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect performance estimation models for design planning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire Retiming for System-on-Chip by Fixpoint Computation
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An Interconnect Channel Design Methodology for High Performance Integrated Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Performance-driven register insertion in placement
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
A method for correcting the functionality of a wire-pipelined circuit
Proceedings of the 41st annual Design Automation Conference
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Proceedings of the 42nd annual Design Automation Conference
A power aware system level interconnect design methodology for latency-insensitive systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Exploiting level sensitive latches in wire pipelining
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimal wire retiming without binary search
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Spec-based flip-flop and latch repeater planning
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Concurrent flip-flop and buffer insertion with adaptive blockage avoidance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Deriving a new efficient algorithm for min-period retiming
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wave-pipelined on-chip global interconnect
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Clustering for processing rate optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A new efficient retiming algorithm derived by formal manipulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clustering for processing rate optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
GALDS: a complete framework for designing multiclock ASICs and socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-chip routing will require multiple clock cycles. Another is the integration of independently clocked components. This paper explores simultaneous routing and buffer insertion in the context of single and multiple clock domains. We present optimal and efficient polynomial algorithms that can be used to estimate communication overhead for interconnect and resource planning in single and multi-clock domain systems. Experimental results verify the correctness and practicality of our approach.