Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimal buffered routing path constructions for single and multiple clock domain systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Concurrent flip-flop and repeater insertion for high performance integrated circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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Given a routing tree for a multi-pin net, two algorithms extending the van Ginneken algorithm [3] for concurrent flip-flop and buffer insertion were presented in [5]. One algorithm called MiLa targets at minimizing the latency, and the other algorithm called GiLa aims to find a feasible solution subject to given latency constraints imposed on sinks. However, they both do not consider the case where buffer/flip-flop blockages are present. In this paper, we enhance the MiLa algorithm and GiLa algorithm to consider blockage avoidance by finding alternative registered-buffered paths between each internal node inside a blockage and its parent node. The experimental results show that in comparison to the MiLa algorithm, our approach is able to find a solution with the same latency (for about half of the test cases) or even better latency (for the remaining test cases) and the same wirelength, while the buffer/flip-flop usage and CPU time are comparable or acceptable. In comparison to the GiLa algorithm, our approach is able to find a feasible solution for each test case while the Gila algorithm fails to do so for several test cases.